Digital signal processing (DSP) may refer to a category of techniques that analyzes signals from sources such as sound, weather satellites and earthquake monitors. These signals are converted into digital data and analyzed using various algorithms such as the fast fourier transform. Once a signal has been reduced to numbers, its components can be isolated, analyzed and rearranged more easily than in analog form. DSP is used in many fields, including biomedicine, sonar, radar, seismology, speech and music processing, imaging and communications.
One technology that uses DSP is a digital subscriber line (DSL). DSL is a technology that increases the digital capacity of ordinary telephone lines (the local loops) into the home or office. DSL speeds are tied to the distance between the customer and the telco central office. At the telco central office, DSL traffic is aggregated in a unit called the DSL Access Multiplexer (DSLAM) and forwarded to the appropriate Internet service provider (ISP) or data network.
In such DSP systems, a single DSP processor core may not have enough processing power to handle the number of necessary calculations to be made. Hence, such systems may implement dedicated hard-wired functions. However, these hard-wired functions require a longer development time and are often not flexible enough to make changes to accommodate evolving international standards. Consequently, there may be a desire in such a system architecture to implement multiple DSP processor cores instead of a single DSP processor core.
Each DSP processor core may be configured to perform operations on real-time and/or asynchronous streamed data. The data may include software “tasks” to be performed by the DSP processor core. A task may refer to operations to be performed by a designated DSP processor core. An example of a task may be to perform layer 2 error correction or perform the fast fourier transform on an incoming digital signal.
An architecture and technique has been developed that allows tasks to communicate with other tasks within a single DSP processor core. Each task may communicate with another task such as acquiring information from that task in order to perform its operation. In such an architecture, each task may have a data structure associated with it, referred to as an inter task control block, used to store status and control information. Each inter task control block may be capable of transmitting its status and control information to another inter task control block thereby allowing each task the ability to communicate its status and control information to another task. Further, in such an architecture, data necessary to perform an operation may be transmitted from one task to another task by a stream connector. Additional details regarding this architecture are disclosed in U.S. Pat. No. 5,625,845, entitled “System for Facilitating Continuous, Real-Time, Unidirectional, and Asynchronous Intertask and End-Device Communication in a Multimedia Data Processing System Using Open Architecture Data Communication Modules,” which is hereby incorporated herein by reference in its entirety.
However, this architecture is limited to tasks communicating with another task in a single DSP processor core. By limiting such communication to a single DSP processor core, DSP systems may be forced to implement a single DSP processor core instead of implementing multiple DSP processor cores. By limiting a system to implementing a single DSP processor core, the system may not have enough processing power to handle the number of necessary calculations to be made.
Therefore, there is a need in the art to facilitate inter-DSP data communications between software tasks located in separate DSP processor cores in a DSP complex.